Transactional Execution: Toward Reliable, High-Performance Multithreading

0272-1732/03/$17.00  2003 IEEE Published by the IEEE computer Society Explicit hardware support for multithreaded software, either in the form of shared-memory chip multiprocessors or hardware multithreaded architectures, is becoming increasingly common. As such support becomes available, application developers are expected to exploit these developments by employing multithreaded programming. But although threads simplify the program’s conceptual design, they also increase programming complexity. In writing sharedmemory multithreaded applications, programmers must ensure that threads interact correctly, and this requires care and expertise. Errors in accessing shared-data objects can cause incorrect program execution and can be extremely subtle. As hardware support for shared-memory applications, we have proposed the use of Transactional Lock Removal (TLR), which ensures high performance while simplifying error-free programming and providing application stability. TLR uses Speculative Lock Elision (SLE) as an enabling mechanism. In SLE, the hardware dynamically identifies synchronization operations, predicts them as being unnecessary, and elides them. By removing these operations, the program behaves as if synchronization were not present. The hardware can then exploit situations that do not require synchronization for a correct execution, and the hardware makes this determination without even performing the synchronization itself. TLR treats a lock-based critical section as a lock-free, optimistic transaction, using SLE to elide the lock, which in turn lets multiple threads enter a critical section protected by the same lock and execute the critical section speculatively. As in SLE, the hardware reads and monitors the lock in a shared state, but ordinarily does not write it. TLR uses the critical shared data itself to order any conflicting data accesses and thus provides successful lock-free execution, even Ravi Rajwar